1. Field of the Invention
This invention generally relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device to enhance the uniformity of the semiconductor device.
2. Description of Related Art
As the line width and the size of the semiconductor device become smaller, it is unavoidable that the polysilicon electrode of the MOSFET and the memory device become smaller. When the integration of the devices increases, the resistance of the source region and the drain region usually increases. However, as the size of the device shrinks and its process margin declines, the uniformity of the semiconductor devices becomes worse.
During the fabrication of the MOSFET, after the gate electrode is formed by patterning a polysilicon layer on a gate dielectric layer, the ion implantation is performed to form the source/drain extension region at the two sides of the gate electrode using the gate dielectric layer to protect the surface of the substrate. Thereafter, a composite silicon oxide/silicon nitride spacer is formed on the sidewalls of the gate after defining the gate electrode. The composite spacer can be formed by forming an offset spacer oxide layer covering the substrate and the gate electrode, forming a spacer silicon nitride layer covering the offset spacer oxide layer and then performing anisotropic etching to remove a portion of spacer silicon nitride layer until the offset spacer oxide layer is exposed. The remaining offset spacer oxide layer can protect the surface of the substrate when performing the ion implantation step to the substrate. Later on, the ion implantation is performed to form the source and drain regions at the two sides of the gate electrode and then the salicide process is performed.
However, when the size of the device and the line-width shrink, the thickness of each layer and the process margin in each layer also become smaller. Especially, when the thickness of the gate dielectric and the offset spacer oxide layer is less than or about 100 Å, the thin offset spacer oxide layer and the gate dielectric layer can easily be overetched and the thickness of the remaining gate dielectric layer and that of the remaining offset oxide layer are not uniform within the wafer. Since the thickness of the gate dielectric layer and the remaining offset spacer oxide layer is varied, the junction depths of the source/drain extension region and that of the source/drain contact region become non-uniform after the ion implantation step through the non-uniform gate dielectric layer and the non-uniform offset spacer oxide layer respectively. In addition to the non-uniform depth of the source/drain extension region and that of the source/drain contact region, the effective channel length of the gate electrode may be changed, which significantly affects the uniformity of the semiconductor devices on the wafer.